1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of securing a low operation voltage of the device by improving the uniformity of an ion implantation layer for controlling the threshold voltage of transistors or memory devices.
2. Background of the Related Art
In order to manufacture the semiconductor devices, an ion implantation process as well as deposition and etch processes must be inevitably implemented.
Of them, a method of manufacturing a flash memory device will be now described in short. A well and an ion implantation layer for controlling the threshold voltage are first sequentially formed in the active region by means of the ion implantation process. A stack structure of a tunnel oxide film and a first polysilicon layer is formed in a pattern vertical to the word line direction. A dielectric film and a second polysilicon layer are then sequentially formed. Next, the second polysilicon layer and the dielectric film are patterned to form a control gate. The first polysilicon layer is then patterned to form a floating gate. Thus, the flash memory device is completed.
In the above, an isolation film is formed, by forming a trench while patterning the first polysilicon layer and the tunnel oxide film through a patterning process and then burying an insulating material, in a state that the tunnel oxide film and the first polysilicon layer are formed and a pad nitride film is formed on the first polysilicon layer. If the isolation film is thus formed by applying a SA-STI (self aligned-shallow trench isolation) structure, it is possible to minimize damage of the tunnel oxide film and the tunnel oxide film from being formed too thinly.
Meanwhile, in case where a high voltage NMOS transistor to be used as a transistor for a X decoder and a cell transistor are manufactured by the above process in a NAND type flash device, a high voltage is applied to a p-well region and a junction region. For this reason, the source/drain junction region is not formed using a common plus junction but formed using a DDD (double doped drain) junction process and a plug ion implantation process. In this DDD junction, however, it is required that the dose of implanted impurity be reduced in order to improve a breakdown voltage characteristic for application of the high voltage. Due to this, not only the operating voltage of below 1.0V required in the transistor is increased but also it is difficult to secure the operating voltage of below 1.0V even with the dose of the impurity implanted in order to control the threshold voltage of the channel region. Also, although the ion implantation layer for controlling the threshold voltage is usually formed using the medium current ion implanter, it is more difficult to secure the operating voltage of below 1.0V in controlling the threshold voltage through the minimum ion implantation necessary for securing uniform ion implantation distribution.